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te ch tm t66h0001a tm technology inc. reserves the right p. 1 publication date: jul. 2002 to change products or specifications without notice. revision:a t66h0001a 240 output lcd segment/common driver ic features number of lcd drive outputs : 240 supply voltage for lcd drive : ( +10.0 to +42.0 v) supply voltage for logic system : ( +2.5 to +5.5 v) low power consumption low output impedance package : 269-pin tcp (tape carrier package) description the t66h0001a is a 240-output segment/common driver ic suitable for driving large/medium scale dot matrix lcd panels, and is used in personal computers/work stations. through the use of sst (super slim tcp) technology, it is ideal for substantially decreasing the size of the frame section of the lcd module. the t66h0001a is good both as a segment driver and a common driver, and it can create a low power consuming, high resolution lcd segment mode: 1. shift clock frequency - 20 mhz (max.) : vdd = +5.0 0.5 v - 15 mhz (max.) : vdd = +3.0 to +4.5 v - 12 mhz (max.) : vdd = +2.5 to +3.0 v 2. adopts a data bus system 3. 4-bit/8-bit parallel input modes are selectable with a mode (md) pin 4. automatic transfer function of an enable signal 5. automatic counting function which, in the chip selection mode, causes the internal clock to be stopped by automatically counting 240 bits of input data 6. line latch circuits are reset when /dispoff low active
te ch tm t66h0001a tm technology inc. reserves the right p. 2 publication date: jul. 2002 to change products or specifications without notice. revision:a common mode: - shift clock frequency: 4 mhz (max.) - built-in 240-bit bi-directional shift register (divisible into 120 bits x 2) - available in single mode (240-bit shift register) or in dual mode (120-bit shift register x 2) a. y1 y240 single mode b. y240 y1 single mode c. y1 y120, y121 y240 dual mode d. y240 y121, y120 y1 dual mode the above 4 shift directions are pin selectable - shift register circuits are reset when /dispoff low active part number examples part no. pkg. description T66H0001A-Y tcp pitch 0.21mm, refer to appendix t66h0001a cog refer to pads list pin connections 269-pin tcp
te ch tm t66h0001a tm technology inc. reserves the right p. 3 publication date: jul. 2002 to change products or specifications without notice. revision:a pin description pin no. symbol i/o description 1 to 240 y1-y240 o lcd drive output 241, 269 v 0l, v 0r - power supply for lcd drive 242, 268 v 12l ,v 12r - power supply for lcd drive 243, 267 v 43l ,v 43r - power supply for lcd drive 244, 266 v 5l ,v 5r - power supply for lcd drive 245 vdd - power supply for logic system (+2.5v to +5.5v) 246 s/c i segment mode/common mode selection 247, 259 eio 2 , eio 1 i/o input/output for chip selection at segment mode/ shift data input/output for shift register at common mode 248 to 254 di 0 -di 6 i display data input at segment mode 255 di 7 i display data input at segment mode/dual mode data input at common mode 256 xck i clock input for taking display data at segment mode 257 /dispoff i control input for output of non-select level 258 lp i latch pules input for display data at segment mode shift clock input for shift register at common mode 260 fr i ac-converting signal input for lcd drive waveform 261 l/r i input for selecting the reading direction of display data at segment mode/input for selecting the shift direction of shift register at common mode 262 md i mode selection input 263, 264 nc i not connection 265 vss - ground(0v)
te ch tm t66h0001a tm technology inc. reserves the right p. 4 publication date: jul. 2002 to change products or specifications without notice. revision:a input/output circuits
te ch tm t66h0001a tm technology inc. reserves the right p. 5 publication date: jul. 2002 to change products or specifications without notice. revision:a
te ch tm t66h0001a tm technology inc. reserves the right p. 6 publication date: jul. 2002 to change products or specifications without notice. revision:a block diagram
te ch tm t66h0001a tm technology inc. reserves the right p. 7 publication date: jul. 2002 to change products or specifications without notice. revision:a functional operations of each block block function active control in case of segment mode, controls the selection or non-selection of the chip. following and lp signal input, and after the chip selection signal is input, a selection signal is generated internally until 240 bits of data have been read in. once data input has been completed, a selection signal for cascade connection is output, and the chip is non-selected. in case of common mode, controls the input/output data of bi-directional pins. sp conversion & data control in case of segment mode, keeps input data which are 2 clocks of xck at 4-bit parallel input mode in latch circuit, or keeps input data which are 1 clock of xck at 8-bit parallel input mode in latch circuit, after that they are put on the internal data 8 bits at a time. data latch control in case of segment mode, selects the state of the data latch which reads in the data bus signals. the shift direction is controlled by the control logic. for every 16 bits of data read in, the selection signal shifts one bit based on the state of the control circuit. data latch in case of segment mode, latches the data on the data bus. the latch state of each lcd rive output pin is controlled by the control logic and the data latch control; 240 bits of data are read in 30 sets of 8 bits. line latch/ shift register in case of segment mode, all 240 bits which have been read into the data latch are simultaneously latched at the falling edge of the lp signal, and are output to the level shifter block. in case of common mode, shifts data from the data input pin at the falling edge of the lp signal. level shifter the logic voltage signal is level-shifted to the lcd drive voltage level, and in output to the driver block. 4-level driver drives the lcd drive output pins from the line latch/shift register data, and selects one of 4 levels (v 0 , v 12 , v 43 , or v 5 ) based on the s/c, fr and /dispoff signals. control logic controls the operation of each block. in case of segment mode, when an lp signal has been input, all blocks are rest and the control logic waits for the selection signal output from the active control block. once the selection signal has been output, operation of the data latch and data transmission is controlled, 240 bits of data are read in, and the chip in non-selected. in case of common mode, controls the direction of data shift.
te ch tm t66h0001a tm technology inc. reserves the right p. 8 publication date: jul. 2002 to change products or specifications without notice. revision:a functional description pin functions (segment mode) symbol function v dd logic system power supply pin, connected to +2.5 to +5.5 v. vss ground pin, connected to 0 v. v 0l , v 0r v 12l , v 12r v 43l , v 43r v 5l , v 5r bias power supply pins for lcd drive voltage ? normally use the bias voltages set by a resistor divider. ? ensure that voltages are set such that vss v 5 < v 43 < v 12 < v 0 . ? v il and v ir ( i= 0 , 12 , 43 , 5) must connect to an external power supply , and supply regular voltage which is assigned by specification for each power pin. di 7 , di 0 input pins for display data ? in 4-bit parallel input mode, input data into the 4 pins, di 3 -di 0 . connect di 7 -di 4 to vss or v dd . ? in 8-bit parallel input mode, input data into the 8 pins, di 7 - di 0 . ? refer to ? relationship between the display data and lcd drive output pins ? in functional operations. xck clock input pin for taking display data ? data is read at the falling edge of the clock pulse. lp latch pulse input pin for display data ? data is latched at the falling edge of the clock pulse. l/r input pin for selecting the reading direction of display data ? when set to vss level ?l?, data is read sequentially from y 240 to y 1 . ? when set to v dd level ?h?, data is read sequentially from y 1 to y 240 . ? refer to ? relationship between the display data and lcd drive output pins ? in functional operations. /dispoff control input pin for output of non-select level ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? when set to vss level ?l?, the lcd drive output pins (y 1 -y 240 ) are set to level v 5 . ? when set to ?l? ,the contents of the line latch are reset , but the display data are read in the data latch regardless of the condition of /dispoff. when the /dispoff function is canceled, the driver outputs non-select level (v 12 or v 43 ), then outputs the contents of the data latch at the next falling edge of the lp. at that time, if /dispoff removal time does not correspond to what is shown in ac characteristics, it can not output the reading data correctly. ? table of truth values is shown in ? truth table ? in functional operations. fr ac signal input pin for lcd drive waveform ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? normally it inputs a frame inversion signal. ? the lcd drive output pins? output voltage levels can be set using the line latch output signal and the fr signal. ? table of truth values is shown in ? truth table ? in functional operations.
te ch tm t66h0001a tm technology inc. reserves the right p. 9 publication date: jul. 2002 to change products or specifications without notice. revision:a symbol function md mode selection pin ? when set to vss level ?l? , 8 bit parallel input mode is set. ? when set to v dd level ?h? , 4 bit parallel input mode is set. ? refer to ? relationship between the display data and lcd drive output pins ? in functional operations. s/c segment mode/common mode selection pin ? when set to v dd level ?h? , segment mode is set. eio 1 , eio 2 input/output pins for chip selection ? when l/r input is at vss level ?l? , eio 1 is set for output , and eio 2 is set for input. ? when l/r input is at v dd level ?h? , eio 1 is set for input , and eio 2 is set for output. ? during output , set to ?h? while lp/xck is ?h? and after 240 bits of data have been read , set to ?l? for one cycle (from falling edge to falling edge of xck), after which it returns to ?h?. ? during input , the chip is selected while ei is set to ?l? after the lp signal is input. the chip is non-selected after 240 bits of data have been read. y 1 -y 240 lcd drive output pins ? corresponding directly to each bit of the data latch , one level (v 0 , v 12 , v 43 , or v 5 ) is selected and output. ? table of truth values is shown in ? truth table ? in functional operations.
te ch tm t66h0001a tm technology inc. reserves the right p. 10 publication date: jul. 2002 to change products or specifications without notice. revision:a common mode: symbol function v dd logic system power supply pin, connected to +2.5 to +5.5 v. vss ground pin, connected to 0 v. v 0l , v 0r v 12l , v 12r v 43l , v 43r v 5l , v 5r bias power supply pins for lcd drive voltage ? normally use the bias voltages set by a resistor divider. ? ensure that voltages are set such that vss v 5 < v 43 < v 12 < v 0 . ? v il and v ir ( i = 0 , 12 , 43 , 5) must connect to an external power supply , and supply regular voltage which is assigned by specification for each power pin. eio 1 shift data input/output pin for bi-directional shift register ? output pin when l/r is at vss level ?l? , input pin when l/r is at v dd level ?h?. ? when l/r = h, eio 1 is used as input pin, it will be pulled down. ? when l/r = l, eio 1 is used as output pin, it won?t be pulled down. ? refer to ? relationship between the display data and lcd drive output pins ? in functional operations. eio 2 shift data input/output pin for bi-directional shift register ? input pin when l/r is at vss level ?l? , output pin when l/r is at v dd level ?h?. ? when l/r = l, eio 2 is used as input pin, it will be pulled down. ? when l/r = h, eio 2 is used as output pin, it won?t be pulled down. ? refer to ? relationship between the display data and lcd drive output pins ? in functional operations. lp latch pulse input pin for display data ? data is latched at the falling edge of the clock pulse. l/r input pin for selecting the shift direction of bi-directional shift register ? data is shifted from y 240 to y 1 when set to vss level ?l? , and data is shifted from y 1 to y 240 when set to v dd level ?h?. ? refer to ? relationship between the display data and lcd drive output pins ? in functional operations. /dispoff control input pin for output of non-select level ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? when set to vss level ?l?, the lcd drive output pins (y 1 -y 240 ) are set to level v 5 . ? when set to ?l?, the contents of the shift register are reset to not reading data. when the /dispoff function is canceled , the driver outputs non-select level (v 12 or v 43 ), and the shift data is read at the next falling edge of the lp. at that time, if dispoff removal time does not correspond to what is shown in ac characteristics, the shift data is not read correctly. ? table of truth values is shown in ? truth table ? in functional operations. fr ac signal input pin for lcd drive waveform ? the input signal is level-shifted from logic voltage level to lcd drive voltage level, and controls the lcd drive circuit. ? normally it inputs a frame inversion signal. ? the lcd drive output pins? output voltage levels can be set using the line latch output signal and the fr signal. ? table of truth values is shown in ? truth table ? in functional operations.
te ch tm t66h0001a tm technology inc. reserves the right p. 11 publication date: jul. 2002 to change products or specifications without notice. revision:a symbol function md mode selection pin ? when set to vss level ?l? , single operation is selected ; when set to v dd level ?h? , dual mode operation is selected. ? refer to ? relationship between the display data and lcd drive output pins ? in functional operations. di 7 dual mode data input pin ? according to the data shift direction of the data shift register , data can be input starting from the 121 st bit. ? when the chip is used in dual mode, di 7 will be pulled down. ? when the chip is used in single mode, di 7 won?t be pulled down. ? refer to ? relationship between the display data and lcd drive output pins ? in functional operations. s/c segment mode/common mode selection pin ? when set to vss level ?l, common mode is set. di 6 -di 0 not used ? connect di 6 -di 0 to vss or v dd , avoiding floating. xck not used ? xck is pulled down in common mode, so connect to vss or open. y 1 -y 240 lcd drive output pins ? corresponding directly to each bit of the data latch , one level (v 0 , v 12 , v 43 , or v 5 ) is selected and output. ? table of truth values is shown in ? truth table ? in functional operations.
te ch tm t66h0001a tm technology inc. reserves the right p. 12 publication date: jul. 2002 to change products or specifications without notice. revision:a functional operations truth table (segment mode) fr latch data /dispoff lcd drive output voltage level (y 1 -y 240 ) l l h v 43 l h h v 5 h l h v 12 h h h v 0 x x l v 5 (common mode) r latch data /dispoff lcd drive output voltage level (y 1 -y 240 ) l l h v 43 l h h v 0 h l h v 12 h h h v 5 x x l v 5 notes : vss <= v 5 < v 43 < v 12 < v 0 , l: vss (0 v), h: v dd (+2.5 to +5.5 v) , x : don?t care ?don?t care? should be fixed to ?h? or ?l?, avoiding floating. there are two kinds of power supply (logic level voltage and lcd drive voltage) for the lcd driver. supply regular voltage which is assigned by specification for each power pin.
te ch tm t66h0001a tm technology inc. reserves the right p. 13 publication date: jul. 2002 to change products or specifications without notice. revision:a relationship between the display data and lcd drive output pins (segment mode) (a) 4-bit parallel input mode number of clocks md l/r eio 1 eio 2 data iinpu t 60 clock 59 clock 58 clock ? 3 clock 2 clock 1 clock di 0 y 1 y 5 y 9 ? y 229 y 233 y 237 di 1 y 2 y 6 y 10 ? y 230 y 234 y 238 di 2 y 3 y 7 y 11 ? y 231 y 235 y 239 h l output input di 3 y 4 y 8 y 12 ? y 232 y 236 y 240 di 0 y 240 y 236 y 232 ? y 12 y 8 y 4 di 1 y 239 y 235 y 231 ? y 11 y 7 y 3 di 2 y 238 y 234 y 230 ? y 10 y 6 y 2 h h input output di 3 y 237 y 233 y 229 ? y 9 y 5 y 1
te ch tm t66h0001a tm technology inc. reserves the right p. 14 publication date: jul. 2002 to change products or specifications without notice. revision:a (b) 8 bit parallel input mode number of clocks md l/r eio 1 eio 2 data iinpu t 30 clock 29 clock 28 clock ? 3 clock 2 clock 1 clock di 0 y 1 y 9 y 17 ? y 217 y 225 y 233 di 1 y 2 y 10 y 18 ? y 218 y 226 y 234 di 2 y 3 y 11 y 19 ? y 219 y 227 y 235 di 3 y 4 y 12 y 20 ? y 220 y 228 y 236 di 4 y 5 y 13 y 21 ? y 221 y 229 y 237 di 5 y 6 y 14 y 22 ? y 222 y 230 y 238 di 6 y 7 y 15 y 23 ? y 223 y 231 y 239 l l output input di 7 y 8 y 16 y 24 ? y 224 y 232 y 240 di 0 y 240 y 232 y 224 ? y 24 y 16 y 8 di 1 y 239 y 231 y 223 ? y 23 y 15 y 7 di 2 y 238 y 230 y 222 ? y 22 y 14 y 6 di 3 y 237 y 229 y 221 ? y 21 y 13 y 5 di 4 y 236 y 228 y 220 ? y 20 y 12 y 4 di 5 y 235 y 227 y 219 ? y 19 y 11 y 3 di 6 y 234 y 226 y 218 ? y 18 y 10 y 2 l h input output di 7 y 233 y 225 y 217 ? y 17 y 9 y 1 (common mode) md l/r data transfer direction eio 1 eio 2 di 7 l y 240 y 1 output input x l (single) h y 1 y 240 input output x y 240 y 121 l y 120 y 1 output input input y 1 y 120 h (dual) h y 121 y 240 input output input notes : ? l : vss (0 v ) , h : v dd (+2.5 to +5.5 v) , x : don ? t care ? don ? t care ? should be fixed to ? h ? or ? l ? , avoiding floating.
te ch tm t66h0001a tm technology inc. reserves the right p. 15 publication date: jul. 2002 to change products or specifications without notice. revision:a connection examples of plural segment drivers (a) when l/r = ?l? (b) when l/r = ?h?
te ch tm t66h0001a tm technology inc. reserves the right p. 16 publication date: jul. 2002 to change products or specifications without notice. revision:a connection examples for plural common drivers (a) single mode (l/r = ?l?) (b) single mode (l/r = ?h?)
te ch tm t66h0001a tm technology inc. reserves the right p. 17 publication date: jul. 2002 to change products or specifications without notice. revision:a (c) dual mode (l/r = ?l?) (d) dual mode (l/r = ?h?)
te ch tm t66h0001a tm technology inc. reserves the right p. 18 publication date: jul. 2002 to change products or specifications without notice. revision:a precautions precautions when connecting or disconnecting the power supply this ic has a high-voltage lcd driver, so it may be permanently damaged by a high current which may flow if voltage is supplied to the lcd drive power supply while the logic system power supply is floating. the details are as follows. ? when connecting the power supply, connect the lcd drive power after connecting the logic system power. furthermore, when disconnecting the power , disconnect the logic system power after disconnecting the lcd drive power. ? it is advisable to connect the serial resister (50 to 100 ? ) or fuse to the lcd drive power v 0 of the system as a current limiter. set up a suitable value of the resister in consideration of the display grade. and when connecting the logic power supply, the logic condition of this ic inside is insecurity. therefore connect the lcd drive power supply after resetting logic condition of this ic inside on /dispoff function. after that, cancel the /dispoff function after the lcd drive power supply has become stable. furthermore, when disconnecting the power , set the lcd drive output pins to level v 5 on /dispoff function. then disconnect the logic system power after disconnecting the lcd drive power. when connecting the power supply, follow the recommended sequence shown here.
te ch tm t66h0001a tm technology inc. reserves the right p. 19 publication date: jul. 2002 to change products or specifications without notice. revision:a absolute maximum ratings parameter symbol applicable pins rating unit note supply voltage(1) v dd v dd -0.3 to +7.0 v v 0 v 0l, v 0r -0.3 to +42.0 v v 12 v 12l, v 12r -0.3 to v 0 + 0.3 v v 43 v 43l, v 43r -0.3 to v 0 + 0.3 v supply voltage(2) v 5 v 5l, v 5r -0.3 to v 0 + 0.3 v input voltage v i di 7- di 0 , xck, lp, l/r, fr, md, s/c, eio 1 , eio 2 , dispoff, test 1, test 2 -0.3 to v dd + 0.3 v 1,2 storage temperature tstg -45 to +125 oc notes : 1. t a = +25 oc 2. the maximum applicable voltage on any pin with respect to vss (0v). recommended operating conditions parameter aymbol applicable pins min. typ. max. unit note supply voltage(1) v dd v dd +2.5 +5.5 v supply voltage(2) v 0 v 0l, v 0r +10.0 +45.0 v 1,2 operating temperature t opr -20 +85 oc notes : 1. the applicable voltage on any pin with respect to vss (0v). 2. ensure that voltage are set such that vss <= v 5 < v 43 < v 12 < v 0 .
te ch tm t66h0001a tm technology inc. reserves the right p. 20 publication date: jul. 2002 to change products or specifications without notice. revision:a electrical characteristics dc characteristics (segment mode) (v ss = v 5 = 0v, v dd = +2.5 to +5.5v, v 0 = +10.0 to +42.0v, t opr = -20 to +85 oc) parameter symbol conditions applicable pins min. typ. max. unit note input ?low? voltage v il 0.2v dd v input ?high? voltage v ih di7-di0, xck, lp, l/r, fr, md, s/c, eio1, eio2, /dispoff 0.8v dd v output ?low? voltage v ol i ol = +0.4ma +0.4 v output ?high? voltage v oh i oh = -0.4ma eio1, eio2 v dd -0.4 v i lil v i = vss -10.0 ua input leakage current i lih v i = v dd di7-di0, xck, lp, l/r, fr, md, s/c, eio1, eio2, /dispoff +10.0 ua vo=40v 1.0 1.5 vo=30v 1.5 2.0 output resistance r on | v on | =0.5v vo=20v y 1 - y 240 2.0 2.5 k standby current i stb v ss 50.0 ua 1 supply current(1) (non-selection) i dd1 v dd 5.0 ma 2 supply current(2) (selection) i dd2 v dd 5.0 ma 3 supply current(3) i o v0l,v0r 700 ua 4 notes : 1. v dd = +5.0v, v 0 = +42.0 v, v i = vss. 2. v dd = +5.0v, v 0 = +42.0 v,f xck = 20 mhz, non-load, e i = v dd . the input data is turned over by data taking clock (4-bit parallel input mode). 3. v dd = +5.0v, v 0 = +42.0 v,f xck = 20 mhz, non-load, e i = vss. the input data is turned over by data taking clock (4-bit parallel input mode). 4. v dd = +5.0v, v 0 = +42.0 v,f xck = 20 mhz, f lp = 41.6 khz, f fr = 80 hz, non-load. the input data is turned over by data taking clock (4-bit parallel input mode).
te ch tm t66h0001a tm technology inc. reserves the right p. 21 publication date: jul. 2002 to change products or specifications without notice. revision:a (common mode) (vss = v5 = 0v, v dd = +2.5 to +5.5v, v 0 = +10.0 to +42.0v, t opr = -20 to +85 oc) parameter symbol conditions applicable pins min. typ. max. unit note input ?low? voltage v il 0.2v dd v input ?high? voltage v ih di7-di0, xck, lp, l/r, fr, md, s/c, eio1, eio2, /dispoff 0.8v dd v output ?low? voltage v ol i ol = +0.4ma +0.4 v output ?high? voltage v oh i oh = -0.4ma eio1, eio2 v dd -0.4 v i lil v i = vss di7-di0, xck, lp, l/r, fr, md, s/c, eio1, eio2, /dispoff -10.0 ua input leakage current i lih v i = v dd di6-di0, lp, l/r, fr, md, s/c, /dispoff +10.0 ua input pull-down current i pd v i = v dd di7, xck, eio1, eio2 100.0 ua vo=40v 1.0 1.5 vo=30v 1.5 2.0 output resistance r on | v on | =0.5v vo=20v y 1 - y 240 2.0 2.5 k standby current i stb vss 50.0 ua 1 supply current(1) i dd v dd 120.0 ua 2 supply current(2) io v0l,v0r 200 ua 2 notes : 1.v dd = +5.0v, v 0 = +42.0 v, v i = vss. 2.v dd = +5.0v, v 0 = +42.0 v,f xck = 20 mhz, f lp = 41.6 khz, f fr = 80 hz, 1/480 duty operation, no-load.
te ch tm t66h0001a tm technology inc. reserves the right p. 22 publication date: jul. 2002 to change products or specifications without notice. revision:a ac characteristics (segment mode 1) (vss = v 5 = 0v, v dd = +5.0 0.5v, v 0 = +10.0 to +42.0v, t opr = -20 to +85 oc) parameter symbol conditions min. typ. max. unit note shift clock period twck t r ,t f 10 ns 50 ns 1 shift clock ?h? pulse width twckh 15 ns shift clock ?l? pulse width twckl 15 ns data setup time t ds 10 ns data hold time t dh 12 ns latch pulse ?h? pulse width t wlph 15 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 30 ns latch pulse rise to shift clock rise time t ls 25 ns latch pulse fall to shift clock fall time t lh 25 ns enable setup time ts 10 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff ?l? pulse width t wdl 1.2 us output delay time (1) t d c l= 15 pf 30 ns output delay time (2) t pd1, t pd2 c l= 15 pf 1.2 us output delay time (3) t pd3 c l= 15 pf 1.2 us notes : 1. takes the cascade connection into consideration 2. (twck - twck h ? twck l )/2 is maximum in the case of high speed operation. (segment mode 2) (vss = v 5 = 0v, v dd = +3.0 to +4.5v, v 0 = +10.0 to +42.0v, t opr = -20 to +85 oc) parameter symbol conditions min. typ. max. unit note shift clock period twck t r ,t f 10 ns 66 ns 1 shift clock ?h? pulse width twckh 23 ns shift clock ?l? pulse width twckl 23 ns data setup time t ds 15 ns data hold time t dh 23 ns latch pulse ?h? pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 50 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns enable setup time ts 15 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff ?l? pulse width t wdl 1.2 us output delay time (1) t d c l= 15 pf 41 ns output delay time (2) t pd1, t pd2 c l= 15 pf 1.2 us output delay time (3) t pd3 c l= 15 pf 1.2 us notes : 1. takes the cascade connection into consideration 2. (twck - twck h ? twck l )/2 is maximum in the case of high speed operation.
te ch tm t66h0001a tm technology inc. reserves the right p. 23 publication date: jul. 2002 to change products or specifications without notice. revision:a (segment mode 3) (vss = v 5 = 0v, v dd = +2.5 to +3.0v, v 0 = +10.0 to +42.0v, t opr = -20 to +85 oc) parameter symbol conditions min. typ. max. unit note shift clock period t wck t r ,t f 10 ns 82 ns 1 shift clock ?h? pulse width t wckh 28 ns shift clock ?l? pulse width t wckl 28 ns data setup time t ds 20 ns data hold time t dh 23 ns latch pulse ?h? pulse width t wlph 30 ns shift clock rise to latch pulse rise time t ld 0 ns shift clock fall to latch pulse fall time t sl 65 ns latch pulse rise to shift clock rise time t ls 30 ns latch pulse fall to shift clock fall time t lh 30 ns enable setup time ts 15 ns input signal rise time t r 50 ns 2 input signal fall time t f 50 ns 2 /dispoff removal time t sd 100 ns /dispoff ?l? pulse width t wdl 1.2 us output delay time (1) t d c l= 15 pf 57 ns output delay time (2) t pd1, t pd2 c l= 15 pf 1.2 us output delay time (3) t pd3 c l= 15 pf 1.2 us notes : 1. takes the cascade connection into consideration 2. (twck - twck h ? twck l )/2 is maximum in the case of high speed operation.
te ch tm t66h0001a tm technology inc. reserves the right p. 24 publication date: jul. 2002 to change products or specifications without notice. revision:a timing chart of segment mode
te ch tm t66h0001a tm technology inc. reserves the right p. 25 publication date: jul. 2002 to change products or specifications without notice. revision:a (common mode ) (vss = v 5 = 0v, v dd = +2.5 to +5.5v, v 0 = +10.0 to +42.0v, t opr = -20 to +85 oc) parameter symbol conditions min. typ. max. unit shift clock period twck t r ,t f 10 ns 250 ns v dd = +5.00.5v 15 ns shift clock ?h? pulse width twck h v dd = +2.5 to+4.5v 30 ns data setup time t su 30 ns data hold time t h 50 ns input signal rise time t r 50 ns input signal fall time t f 50 ns /dispoff removal time t sd 100 ns /dispoff ?l? pulse width t wdl 1.2 us output delay time (1) t dl c l = 15 pf 200 ns output delay time (2) t pd1 ,t pd2 c l = 15 pf 1.2 us output delay time (3) t pd3 c l = 15 pf 1.2 us
te ch tm t66h0001a tm technology inc. reserves the right p. 26 publication date: jul. 2002 to change products or specifications without notice. revision:a timing chart of common mode
te ch tm t66h0001a tm technology inc. reserves the right p. 27 publication date: jul. 2002 to change products or specifications without notice. revision:a timing chart of 4-device cascade connection of segment drivers
te ch tm t66h0001a tm technology inc. reserves the right p. 28 publication date: jul. 2002 to change products or specifications without notice. revision:a system configuration example
te ch tm t66h0001a tm technology inc. reserves the right p. 29 publication date: jul. 2002 to change products or specifications without notice. revision:a pads list ?d? means dummy pads which are floating inside the chip. pad size : outpad = 55x72(pad 1 to pad 240) inpad = 70x72(pad 241 to pad 295) dummy = 70x80 open window : outpad = 29x46 inpad = 44x46 dummy = 44x54 bump size : outpad = 43x60 inpad = 54x56 dummy = 54x64 bump height = 18 die size = 14900 x 1070 (without scribe line) scribe line = 80 unit = um pad1 pad240 pad241 pad295 t66h0001a d d d d d d d d d d d d
te ch tm t66h0001a tm technology inc. reserves the right p. 30 publication date: jul. 2002 to change products or specifications without notice. revision:a pad no. pin name x y pad no. pin name x y 1 y1 7185.95 418.4 38 y38 4965.95 418.4 2 y2 7125.95 418.4 39 y39 4905.95 418.4 3 y3 7065.95 418.4 40 y40 4845.95 418.4 4 y4 7005.95 418.4 41 y41 4785.95 418.4 5 y5 6945.95 418.4 42 y42 4725.95 418.4 6 y6 6885.95 418.4 43 y43 4665.95 418.4 7 y7 6825.95 418.4 44 y44 4605.95 418.4 8 y8 6765.95 418.4 45 y45 4545.95 418.4 9 y9 6705.95 418.4 46 y46 4485.95 418.4 10 y10 6645.95 418.4 47 y47 4425.95 418.4 11 y11 6585.95 418.4 48 y48 4365.95 418.4 12 y12 6525.95 418.4 49 y49 4305.95 418.4 13 y13 6465.95 418.4 50 y50 4245.95 418.4 14 y14 6405.95 418.4 51 y51 4185.95 418.4 15 y15 6345.95 418.4 52 y52 4125.95 418.4 16 y16 6285.95 418.4 53 y53 4065.95 418.4 17 y17 6225.95 418.4 54 y54 4005.95 418.4 18 y18 6165.95 418.4 55 y55 3945.95 418.4 19 y19 6105.95 418.4 56 y56 3885.95 418.4 20 y20 6045.95 418.4 57 y57 3825.95 418.4 21 y21 5985.95 418.4 58 y58 3765.95 418.4 22 y22 5925.95 418.4 59 y59 3705.95 418.4 23 y23 5865.95 418.4 60 y60 3645.95 418.4 24 y24 5805.95 418.4 61 y61 3585.95 418.4 25 y25 5745.95 418.4 62 y62 3525.95 418.4 26 y26 5685.95 418.4 63 y63 3465.95 418.4 27 y27 5625.95 418.4 64 y64 3405.95 418.4 28 y28 5565.95 418.4 65 y65 3345.95 418.4 29 y29 5505.95 418.4 66 y66 3285.95 418.4 30 y30 5445.95 418.4 67 y67 3225.95 418.4 31 y31 5385.95 418.4 68 y68 3165.95 418.4 32 y32 5325.95 418.4 69 y69 3105.95 418.4 33 y33 5265.95 418.4 70 y70 3045.95 418.4 34 y34 5205.95 418.4 71 y71 2985.95 418.4 35 y35 5145.95 418.4 72 y72 2925.95 418.4 36 y36 5085.95 418.4 73 y73 2865.95 418.4 37 y37 5025.95 418.4 74 y74 2805.95 418.4
te ch tm t66h0001a tm technology inc. reserves the right p. 31 publication date: jul. 2002 to change products or specifications without notice. revision:a pad no. pin name x y pad no. pin name x y 75 y75 2745.95 418.4 112 y112 525.95 418.4 76 y76 2685.95 418.4 113 y113 465.95 418.4 77 y77 2625.95 418.4 114 y114 405.95 418.4 78 y78 2565.95 418.4 115 y115 345.95 418.4 79 y79 2505.95 418.4 116 y116 285.95 418.4 80 y80 2445.95 418.4 117 y117 225.95 418.4 81 y81 2385.95 418.4 118 y118 165.95 418.4 82 y82 2325.95 418.4 119 y119 105.95 418.4 83 y83 2265.95 418.4 120 y120 45.95 418.4 84 y84 2205.95 418.4 121 y121 -46.25 418.4 85 y85 2145.95 418.4 122 y122 -106.25 418.4 86 y86 2085.95 418.4 123 y123 -166.25 418.4 87 y87 2025.95 418.4 124 y124 -226.25 418.4 88 y88 1965.95 418.4 125 y125 -286.25 418.4 89 y89 1905.95 418.4 126 y126 -346.25 418.4 90 y90 1845.95 418.4 127 y127 -406.25 418.4 91 y91 1785.95 418.4 128 y128 -466.25 418.4 92 y92 1725.95 418.4 129 y129 -526.25 418.4 93 y93 1665.95 418.4 130 y130 -586.25 418.4 94 y94 1605.95 418.4 131 y131 -646.25 418.4 95 y95 1545.95 418.4 132 y132 -706.25 418.4 96 y96 1485.95 418.4 133 y133 -766.25 418.4 97 y97 1425.95 418.4 134 y134 -826.25 418.4 98 y98 1365.95 418.4 135 y135 -886.25 418.4 99 y99 1305.95 418.4 136 y136 -946.25 418.4 100 y100 1245.95 418.4 137 y137 -1006.25 418.4 101 y101 1185.95 418.4 138 y138 -1066.25 418.4 102 y102 1125.95 418.4 139 y139 -1126.25 418.4 103 y103 1065.95 418.4 140 y140 -1186.25 418.4 104 y104 1005.95 418.4 141 y141 -1246.25 418.4 105 y105 945.95 418.4 142 y142 -1306.25 418.4 106 y106 885.95 418.4 143 y143 -1366.25 418.4 107 y107 825.95 418.4 144 y144 -1426.25 418.4 108 y108 765.95 418.4 145 y145 -1486.25 418.4 109 y109 705.95 418.4 146 y146 -1546.25 418.4 110 y110 645.95 418.4 147 y147 -1606.25 418.4 111 y111 585.95 418.4 148 y148 -1666.25 418.4
te ch tm t66h0001a tm technology inc. reserves the right p. 32 publication date: jul. 2002 to change products or specifications without notice. revision:a pad no. pin name x y pad no. pin name x y 149 y149 -1726.25 418.4 186 y186 -3946.25 418.4 150 y150 -1786.25 418.4 187 y187 -4006.25 418.4 151 y151 -1846.25 418.4 188 y188 -4066.25 418.4 152 y152 -1906.25 418.4 189 y189 -4126.25 418.4 153 y153 -1966.25 418.4 190 y190 -4186.25 418.4 154 y154 -2026.25 418.4 191 y191 -4246.25 418.4 155 y155 -2086.25 418.4 192 y192 -4306.25 418.4 156 y156 -2146.25 418.4 193 y193 -4366.25 418.4 157 y157 -2206.25 418.4 194 y194 -4426.25 418.4 158 y158 -2266.25 418.4 195 y195 -4486.25 418.4 159 y159 -2326.25 418.4 196 y196 -4546.25 418.4 160 y160 -2386.25 418.4 197 y197 -4606.25 418.4 161 y161 -2446.25 418.4 198 y198 -4666.25 418.4 162 y162 -2506.25 418.4 199 y199 -4726.25 418.4 163 y163 -2566.25 418.4 200 y200 -4786.25 418.4 164 y164 -2626.25 418.4 201 y201 -4846.25 418.4 165 y165 -2686.25 418.4 202 y202 -4906.25 418.4 166 y166 -2746.25 418.4 203 y203 -4966.25 418.4 167 y167 -2806.25 418.4 204 y204 -5026.25 418.4 168 y168 -2866.25 418.4 205 y205 -5086.25 418.4 169 y169 -2926.25 418.4 206 y206 -5146.25 418.4 170 y170 -2986.25 418.4 207 y207 -5206.25 418.4 171 y171 -3046.25 418.4 208 y208 -5266.25 418.4 172 y172 -3106.25 418.4 209 y209 -5326.25 418.4 173 y173 -3166.25 418.4 210 y210 -5386.25 418.4 174 y174 -3226.25 418.4 211 y211 -5446.25 418.4 175 y175 -3286.25 418.4 212 y212 -5506.25 418.4 176 y176 -3346.25 418.4 213 y213 -5566.25 418.4 177 y177 -3406.25 418.4 214 y214 -5626.25 418.4 178 y178 -3466.25 418.4 215 y215 -5686.25 418.4 179 y179 -3526.25 418.4 216 y216 -5746.25 418.4 180 y180 -3586.25 418.4 217 y217 -5806.25 418.4 181 y181 -3646.25 418.4 218 y218 -5866.25 418.4 182 y182 -3706.25 418.4 219 y219 -5926.25 418.4 183 y183 -3766.25 418.4 220 y220 -5986.25 418.4 184 y184 -3826.25 418.4 221 y221 -6046.25 418.4 185 y185 -3886.25 418.4 222 y222 -6106.25 418.4
te ch tm t66h0001a tm technology inc. reserves the right p. 33 publication date: jul. 2002 to change products or specifications without notice. revision:a pad no. pin name x y pad no. pin name x y 223 y223 -6166.25 418.4 260 di1 -3398.05 -454 224 y224 -6226.25 418.4 261 di2 -3292.95 -454 225 y225 -6286.25 418.4 262 di2 -3189.45 -454 226 y226 -6346.25 418.4 263 di3 -3058.05 -454 227 y227 -6406.25 418.4 264 di3 -2954.55 -454 228 y228 -6466.25 418.4 265 di4 2596.4 -454 229 y229 -6526.25 418.4 266 di4 2699.9 -454 230 y230 -6586.25 418.4 267 di5 2805 -454 231 y231 -6646.25 418.4 268 di5 2908.5 -454 232 y232 -6706.25 418.4 269 di6 3039.9 -454 233 y233 -6766.25 418.4 270 di6 3143.4 -454 234 y234 -6826.25 418.4 271 di7 3248.5 -454 235 y235 -6526.25 418.4 272 di7 3352 -454 236 y236 -6586.25 418.4 273 xck 3483.4 -454 237 y237 -6646.25 418.4 274 xck 3586.9 -454 238 y238 -6706.25 418.4 275 dispoff 3692 -454 239 y239 -6766.25 418.4 276 dispoff 3795.5 -454 240 y240 -6826.25 418.4 277 lp 3926.9 -454 241 v0l -7154.4 -454 278 lp 4030.4 -454 242 v0l -7069.4 -454 279 eio1 4135.5 -454 243 v12l -6934 -454 280 eio1 4239 -454 244 v12l -6849 -454 281 fr 4370.4 -454 245 v43l -6713.6 -454 282 fr 4473.9 -454 246 v43l -6628.6 -454 283 lr24 4616.9 -454 247 v5l -6493.2 -454 284 lr24 4720.4 -454 248 v5l -6408.2 -454 285 md 4880.85 -454 249 gnd -5043.05 -454 286 gnd 5069.45 -454 250 gnd -4958.05 -454 287 gnd 5154.45 -454 251 vdd -4454.3 -454 288 v5r 6408.2 -454 252 vdd -4369.3 -454 289 v5r 6493.2 -454 253 sc -4179.95 -454 290 v43r 6628.6 -454 254 sc -4076.45 -454 291 v43r 6713.6 -454 255 eio2 -3945.05 -454 292 v12r 6849 -454 256 eio2 -3841.55 -454 293 v12r 6934 -454 257 di0 -3736.45 -454 294 v0r 7069.4 -454 258 di0 -3632.95 -454 295 v0r 7154.4 -454 259 di1 -3501.55 -454
te ch tm t66h0001a tm technology inc. reserves the right p. 34 publication date: jul. 2002 to change products or specifications without notice. revision:a pad no. pin name x y dummy rt 7370 339.75 7291.35 449.85 lt -7291.35 449.85 -7370 339.75 lb -7370 -360.4 -7274.5 -449.85 middle -2355.85 -449.85 -2137 -449.85 -1674.8 -449.85 2356.45 -449.85 rb 7274.5 -449.85 7370 -360.4 appendix:

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